Field-effect transistors (FETs) in semiconductor devices are often manufactured such that either a compressive strain or a tensile strain is applied to the FET channels. This strain, if applied in appropriate directions, can enhance FET performance. N-type FETs (NFETs) can be enhanced through appropriately directed tensile strain, whereas P-type FETs (PFETs) can be enhanced through appropriately directed compressive strain.
Conventionally, strain is produced either by embedding stress-inducing materials, such as silicon-germanium, into the silicon on opposing sides of the FET channel, or by forming a strain-inducing layer over the FET, such as a doped silicon nitride layer. Although these techniques can be used to apply either tensile or compressive strain on a FET channel, there are practical limits to the amount of strain that can be applied using these techniques.
Moreover, the strain supplied by these techniques is not always directed as efficiently as desirable to the FET channel. The strain is often diluted, canceled out, and/or dispersed to other regions of the semiconductor device.
In addition, these techniques do not always work well and can be expensive to implement in mixed-technology semiconductor devices, such as those that contain both silicon-on-oxide (SOI) regions and hybrid orientation technology (HOT) regions.